Publications

Deep Neural Networks (DNNs) have gained widespread adoption in various fields; however, their computational cost is often prohibitively high due to the large number of layers and neurons communicating with each other. Furthermore, DNNs can consume a significant amount of energy due to the large volume of data movement and computation they require. To address these challenges, there is a need for new architectures to accelerate DNNs. In this paper, we propose novel neuron grouping and mapping methods for 2D-mesh Network-on-Chip (NoC)-based DNN accelerators considering both fully connected and partially connected DNN models. We present Integer Linear Programming (ILP) and simulated annealing (SA)-based neuron grouping solutions with the objective of minimizing the total volume of data communication among the neuron groups. After determining a suitable graph representation of the DNN, we also apply ILP and SA methods to map the neurons onto a 2D-mesh NoC fabric with the objective of minimizing the total communication cost of the system. We conducted several experiments on various benchmarks and DNN models with different pruning ratios and achieved an average of 40-50% improvement in communication cost.

@article{NACAR2024104949,
    title = {Neuron grouping and mapping methods for 2D-mesh NoC-based DNN accelerators},
    journal = {Journal of Parallel and Distributed Computing},
    volume = {193},
    pages = {104949},
    year = {2024},
    issn = {0743-7315},
    doi = {https://doi.org/10.1016/j.jpdc.2024.104949},
    url = {https://www.sciencedirect.com/science/article/pii/S0743731524001138},
    author = {Furkan Nacar and Alperen Cakin and Selma Dilek and Suleyman Tosun and Krishnendu Chakrabarty}
}

Summary Integrated circuits have become more vulnerable to soft errors due to smaller transistor sizes and lower threshold voltage levels. Energy reduction methods make circuits more error-prone since even the smallest amounts of environmental radiation can cause a bit flip. Furthermore, redundancy-based error detection and correction methods induce higher costs and area overhead. Thus, several conflicting parameters may need to be considered during embedded system design (e.g., area, performance, energy, and reliability). High-level synthesis (HLS) is the most practical design step to consider all these parameters as complexity increases at lower levels. HLS can be viewed as a multi-objective optimization problem of finding a set of Pareto-optimal designs, allowing designers to choose the ones that best fit the requirements. Moreover, the number of synthesis options superlinearly affects the search space growth, necessitating efficient optimization methods. In this study, we propose simulated annealing (SA)-based HLS methods for multi-Vcc application-specific integrated circuit design, aiming to optimize energy consumption and reliability under the area and latency constraints. Furthermore, we use duplication to improve design reliability as much as the constraints allow. We compared our methods against genetic algorithm (GA)-based and integer linear programming (ILP)-based methods and showed their effectiveness in finding optimum or near-optimum results in a short running time. SA-based methods achieved up to 21.20\% reliability improvement on average and up to 38\% energy reduction on average, while preserving the reliability value against the GA-based metaheuristic counterpart under joint reliability and energy optimization on four HLS benchmarks.

@article{https://doi.org/10.1002/cta.3666,
    author = {Dilek, Selma and Tosun, Suleyman and Cakin, Alperen},
    title = {Simulated annealing-based high-level synthesis methodology for reliable and energy-aware   application specific integrated circuit designs with multiple supply voltages},
    journal = {International Journal of Circuit Theory and Applications},
    volume = {51},
    number = {10},
    pages = {4897-4938},
    keywords = {application-specific integrated circuits, energy, high-level synthesis, modular redundancy, optimization, reliability, simulated annealing, soft errors, voltage islands},
    doi = {https://doi.org/10.1002/cta.3666},
    url = {https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.3666},
    eprint = {https://onlinelibrary.wiley.com/doi/pdf/10.1002/cta.3666},
    year = {2023}
}